1. Field of the Invention
Example embodiments relate to a semiconductor memory device and an operating method thereof and, more particularly, to a semiconductor memory device for storing data and an operating method thereof.
2. Description of the Related Art
In a NAND flash memory device, a plurality of word lines are arranged between a drain select line and a source select line, and a plurality of memory cells are coupled to each of the word lines. A string coupled between a bit line and a common source line includes a drain select transistor, the plurality of memory cells, and a source select transistor. The drain of the drain select transistor is coupled to the bit line, and the gate of the drain select transistor is coupled to the drain select line. The source of the source select transistor is coupled to the common source line, and the gate of the source select transistor is coupled to the drain select line. The plurality of memory cells is coupled in series between the drain select transistor and the source select transistor, and the gates (that is, control gates) of the memory cells are coupled to the respective word lines. Here, the memory cells are placed on the same column.
In a program operation for storing data, a program voltage is supplied to a word line selected from the word lines. Some of the memory cells coupled to the selected word line are designated as program-inhibited cells depending on data stored in the designated memory cells. Threshold voltages of the program-inhibited cells should not be shifted even if a program voltage is supplied to the program-inhibited cells. A method of preventing the threshold voltages of the program-inhibited cells from shifting is described below.
A program inhibition voltage is supplied to a bit line electrically coupled to a program-inhibited cell, and the channel region of the program-inhibited cell is precharged to the program inhibition voltage. Next, a pass voltage is supplied to the word lines, and a program voltage is then supplied to a selected word line. The channel voltage of the program-inhibited cell is boosted by the pass voltage. Consequently, the threshold voltage of the program-inhibited cell is not shifted because a difference between the boosted channel voltage and the program voltage supplied to the word lines is small.
As described above, the channel voltage of the program-inhibited cell needs to be uniformly raised by channel boosting in all the word lines. The resulting boosted channel voltage, however, changes depending on the position of the word line, which may lead to an error. This is described below.
The number of fail bits for memory cells coupled to a first word line adjacent to the source select line is decreased as a level of the pass voltage supplied to the remaining word lines in a program operation is raised. This problem is created because a channel potential is low at the time of the channel boosting. Furthermore, the number of fail bits for memory cells coupled to the last word line adjacent to the drain select line is decreased as a level of the pass voltage supplied to the remaining word lines in a program operation is lowered. This problem is created because a channel potential is high at the time of the channel boosting.
That is, the number of fail bits (or error bits) is increased because conditions of the channel boosting are fixed, but a degree of the boosted channel voltage is varied depending on the position of a word line between the drain select line and the source select line at the time of the channel boosting.